Memory is primarily classified into two types in terms of its function; ROM (Read Only Memory) and RAM (Random Access Memory). Moreover, RAM has two subcategories: SRAM (Static RAM) and DRAM (Dynamic RAM). DRAM generally has a lower access speed and more complicated control circuits than SRAM but is cheaper and has a higher capacity than SRAM, and accordingly, it is widely used primarily in personal computers and other consumer-electronics products. For example, DRAM is used as data error correction memory and buffer memory in reproducing apparatuses using the CD (Compact Disc) and DVD (Digital Video Disc) formats.
As described previously, since DRAM has the disadvantage that it is generally slower than SRAM in access time and cycle time, its access speed is improved using a fast access mode called page mode, i.e., for increasing an effective access time. DRAM is read out in the following order. A word line is selected from a row address and all data of memory cells connected to the word line is sent to a sense amplifier. Next, some of sense amplifiers are selected by a column address and the data is sent to an output buffer. Accordingly, after the output of the sense amplifiers has been determined, data of another memory cell can be accessed by simply changing the column address. In the page mode, in which access is made by changing a column address, data is only sent from a sense amplifier to an output pin, so that access time is reduced in comparison with normal cycles.
A sort of DRAM provided with additional functions to speed up access time and cycle time is SDRAM (Synchronous DRAM). More particularly, SDRAM is a DRAM which configures an interface with a synchronous circuit so that data can be continuously inputted and outputted synchronously with an external clock to provide high-speed data transfer. Operation control is carried out by commands consisting of a combination of RAS (Row Address Strobe), CAS (Column Address Strobe), and WE (Write Enable), and further, command input and data input-output all synchronize with the external clock. The burst mode allows data to be continuously inputted and outputted synchronously with the clock. Moreover, the memory is split into two or four banks (areas), each of which can be controlled independently. Since normal DRAM is configured with one bank, a change of a row address always requires a precharge time, and for the duration of such precharge, data output must be stopped. Since SDRAM has a plurality of banks, if two banks, e.g., are alternately accessed, precharge time can be effectively hidden which has been so far required during switching of row addresses. More particularly, FIG. 11 shows an example of bank switching, and more specifically, shows a comparison of non-bank-switching (upper portion of FIG. 11) and bank switching (lower portion of FIG. 11). Precharge time (cross-hatched areas designated with a "P") exists whether banks are switched or not, but when banks are switched, precharge time is hidden by alternately accessing two banks.
Turning now to discussion of problems in the art, DRAM has the disadvantage that it is generally slower than SRAM in access time and cycle time, and the fast access mode described previously is provided to improve access speed. However, the fast access mode described previously requires a condition of identical row addresses.
The following describes an example of DRAM used as an error correction memory of a DVD reproducing apparatus. More particularly, FIG. 12 shows a DVD error correction block. Error correction codes employed in DVD are CIRC (Cross Interleave Reed-Solomon Code) which is also used in CD and DAT, etc., and which provides a high correction capability by using both inner code parity PI (Parity Inner) and outer code parity PO (Parity Outer). The data is separated on a byte basis and is provided with an identification address to form a sector, and a matrix is formed by a collection of 16 sectors. The second error correction code (PO code) is appended to the data in a column direction and a first error correction code (PI code) is appended to both the data in a row direction and also to the PO code. One sector has 2K bytes of data, while one correction block which occupies 16 sectors is comprised of 32K bytes of data and error correction codes PI and PO. To correct errors, the data and error correction codes must be temporarily stored in memory before being read out for each of the PI and PO series.
In this case, if the data is written to DRAM so that the data in the PI series, for example, has identical row addresses, the data in the PI series can be read out fast by simply changing column addresses after first specifying a row address. However, the data in the PO series cannot be read out fast because all pieces of the data have different row addresses, i.e., precharge is required for any row address change. On the other hand, if the data is written to DRAM so that the data in the PO series has identical row addresses, although the data in the PO series can be read out fast, the data in the PI series cannot be read out fast.
As described above, there is the problem that, when errors are corrected using DRAM, data in the PI and PO series cannot be read out at equal speeds, i.e., one of the PI and PO series reads out faster, so that the overall transfer speed cannot be remarkably improved.
As further background, attention is directed to Parris et al. (U.S. Pat. No. 5,671,392).